<code>

-- Data is displayed for 8 banks, which are serviced from 4 multi region clocks

-- Bank 12 uses Bank 11 mulit-region clock 
-- Bank 11 uses Bank 11 mulit-region clock 
-- Bank 10 uses Bank 11 mulit-region clock 

-- Bank 18 uses Bank 17 mulit-region clock 
-- Bank 17 uses Bank 17 mulit-region clock 
-- Bank 16 uses Bank 17 mulit-region clock 

-- Bank 35 uses Bank 35 mulit-region clock 

-- Bank 30 uses Bank 30 mulit-region clock 


-- data_input( * ) indices are the register numbers

-- Each group of data_input( * ) counts is separated from other groups by blank lines

-- Bank 12 in the DUT
-- The clock in Bank 12 comes from the Bank 11 mulit-region clock 

                                      SNGL_bus(     55  )   <=      data_output(   0  )      ; 
                                      SNGL_bus(     45  )   <=      data_output(   1  )      ; 
                                      SNGL_bus(     48  )   <=      data_output(   2  )      ;
        
        data_input(    0  )   <=      SNGL_bus(     47  )      ;
        data_input(    1  )   <=      SNGL_bus(     43  )      ; 
        data_input(    2  )   <=      SNGL_bus(     44  )      ;

        data_input(    3  )   <=      SNGL_bus(     83  )      ;
        data_input(    4  )   <=      SNGL_bus(     53  )      ; 
        data_input(    5  )   <=      SNGL_bus(     54  )      ;

        data_input(    6  )   <=      SNGL_bus(     49  )      ;
        data_input(    7  )   <=      SNGL_bus(    119  )      ; 
        data_input(    8  )   <=      SNGL_bus(    121  )      ; 

-- Bank 11 in the DUT
-- The clock in Bank 11 comes from the Bank 11 mulit-region clock 

                                      SNGL_bus(     72  )   <=      data_output(   9  )      ; 
                                      SNGL_bus(     89  )   <=      data_output(  10  )      ;
                                      SNGL_bus(     46  )   <=      data_output(  11  )      ;    

        data_input(    9  )   <=      SNGL_bus(     73  )      ; 
        data_input(   10  )   <=      SNGL_bus(     64  )      ;
        data_input(   11  )   <=      SNGL_bus(     65  )      ; 

        data_input(   12  )   <=      SNGL_bus(     84  )      ; 
        data_input(   13  )   <=      SNGL_bus(     50  )      ; 
        data_input(   14  )   <=      SNGL_bus(     93  )      ; 

        data_input(   15  )   <=      SNGL_bus(    115  )      ; -- End   of 1st column
        data_input(   16  )   <=      SNGL_bus(    104  )      ; -- Start of 2nd column
        data_input(   17  )   <=      SNGL_bus(    105  )      ;

-- Bank 10 in the DUT
-- The clock in Bank 10 comes from the Bank 11 mulit-region clock 

                                      SNGL_bus(     81  )   <=      data_output(  18  )      ; 
                                      SNGL_bus(     70  )   <=      data_output(  19  )      ;
                                      SNGL_bus(     58  )   <=      data_output(  20  )      ;    

        data_input(   18  )   <=      SNGL_bus(     82  )      ; 
        data_input(   19  )   <=      SNGL_bus(     76  )      ;
        data_input(   20  )   <=      SNGL_bus(     77  )      ;

        data_input(   21  )   <=      SNGL_bus(     71  )      ; 
        data_input(   22  )   <=      SNGL_bus(     62  )      ; 
        data_input(   23  )   <=      SNGL_bus(     63  )      ;

        data_input(   24  )   <=      SNGL_bus(     59  )      ;
        data_input(   25  )   <=      SNGL_bus(     51  )      ;
        data_input(   26  )   <=      SNGL_bus(     52  )      ;


-- Bank 18 in the DUT
-- The clock in Bank 18 comes from the Bank 17 mulit-region clock 

                                      SNGL_bus(     23  )   <=      data_output(  27  )      ; 

        data_input(   27  )   <=      SNGL_bus(     24  )      ; 
        data_input(   28  )   <=      SNGL_bus(    111  )      ;
        data_input(   29  )   <=      SNGL_bus(    112  )      ;
        data_input(   30  )   <=      SNGL_bus(    109  )      ; 

        
-- Bank 35 in the DUT
-- The clock in Bank 35 comes from the Bank 35 mulit-region clock 

                                      SNGL_bus(     34  )   <=      data_output(  31  )      ; 

        data_input(   31  )   <=      SNGL_bus(     16  )      ; -- End   of 2nd column
        data_input(   32  )   <=      SNGL_bus(     40  )      ; -- Start of 3rd column
        data_input(   33  )   <=      SNGL_bus(    134  )      ;
        data_input(   34  )   <=      SNGL_bus(    141  )      ; 


-- Bank 17 in the DUT
-- The clock in Bank 17 comes from the Bank 17 mulit-region clock 

                                      SNGL_bus(     21  )   <=      data_output(  35  )      ; 
                                      SNGL_bus(     10  )   <=      data_output(  36  )      ;

        data_input(   35  )   <=      SNGL_bus(     22  )      ; 
        data_input(   36  )   <=      SNGL_bus(     12  )      ;
        data_input(   37  )   <=      SNGL_bus(     13  )      ;

        data_input(   38  )   <=      SNGL_bus(     41  )      ; 
        data_input(   39  )   <=      SNGL_bus(      4  )      ; 
        data_input(   40  )   <=      SNGL_bus(      5  )      ;


-- Bank 16 in the DUT
-- The clock in Bank 16 comes from the Bank 17 mulit-region clock 

                                      SNGL_bus(     80  )   <=      data_output(  41  )      ; 
                                      SNGL_bus(     56  )   <=      data_output(  42  )      ;
                                      SNGL_bus(     30  )   <=      data_output(  43  )      ;    

        data_input(   41  )   <=      SNGL_bus(     85  )      ; 
        data_input(   42  )   <=      SNGL_bus(     68  )      ;
        data_input(   43  )   <=      SNGL_bus(     69  )      ;
        
        data_input(   44  )   <=      SNGL_bus(     57  )      ; 
        data_input(   45  )   <=      SNGL_bus(    139  )      ; 
        data_input(   46  )   <=      SNGL_bus(     39  )      ;
        
        data_input(   47  )   <=      SNGL_bus(     33  )      ; -- End   of 3rd column
        data_input(   48  )   <=      SNGL_bus(     28  )      ; -- Start of 4th column
        data_input(   49  )   <=      SNGL_bus(     29  )      ;

-- Bank 30 in the DUT
-- The clock in Bank 30 comes from the Bank 30 mulit-region clock 

                                      SNGL_bus(     53  )   <=      data_output(  53  )      ; 
                                      SNGL_bus(     66  )   <=      data_output(  54  )      ;

        data_input(   50  )   <=      SNGL_bus(     75  )      ; 
        data_input(   51  )   <=      SNGL_bus(     60  )      ;
        data_input(   52  )   <=      SNGL_bus(     61  )      ;
        
        data_input(   53  )   <=      SNGL_bus(     67  )      ; 
        data_input(   54  )   <=      SNGL_bus(     78  )      ; 
        data_input(   55  )   <=      SNGL_bus(     79  )      ;

</code>